Cadence JasperGold 24.03

Description

Cadence JasperGold 24.03 for linux

Key Benefits

  • Finds more bugs in less time, earlier in the design process, compared to other verification methods
  • Machine learning-enabled Smart Proof technology for 2X faster proofs out of the box and 5X faster regressions
  • Advanced design scalability for 2X design capacity increase and 50% memory footprint reduction
  • Signoff-accurate formal coverage with intuitive analysis GUI
  • Eases debug and what-if analysis

The Cadence® Jasper™ RTL Apps feature machine learning technology and core formal technology enhancements.

Smart Proof Technology

The Jasper RTL Apps represent the latest stage of ongoing proof-solver algorithm and orchestration improvements. They incorporate Smart Proof technology to improve verification throughput, while machine learning is used to select and parameterize solvers to enable faster first-time proofs. Additionally, machine learning is used to optimize successive runs for regression testing, either on premises or in the cloud. With Smart Proof technology, proofs speed up on average by 2X out of the box and by 5X on regression runs.

Advanced Design Scalability

Given today’s larger and more complex SoC designs, the design compilation process sets the maximum size of design, and the compute resources necessary, to start formal analysis. The Jasper RTL Apps deliver more than 2X design compilation capacity with an average of 50% reduction in memory usage during compilation. Additionally, engineers can effectively scale design capacity through advanced parallel compilation technologies that optimally use available compute resources and run proofs in the cloud.

Formal Signoff Enhancements

Formal coverage technologies let engineers perform IP signoff purely within the Jasper RTL Apps. These formal signoff technologies include improved proof-core and checker coverage accuracy, techniques to derive meaningful coverage from deep bug hunting, and formal coverage analysis views. Ease your debug and what-if analysis with the powerful Jasper Visualize™ Interactive Debug Environment incorporating the QuietTrace™ debugging capability. Together, those features deliver signoff-quality formal coverage metrics and enable multi-engine chip-level verification closure.

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