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he Olympus-SoC™ Netlist-to-GDSII system comprehensively addresses the performance, capacity, time-to-market, power, and variability challenges encountered at the leading-edge process nodes. It is a complete physical design implementation tool for the complex multi-patterning and FinFET requirements of advanced process technologies. Olympus-SoC provides the highest capacity in the industry, with a very compact and scalable database capable of handling designs with hundreds of millions of instances. Its low-power suite enables both leakage and dynamic power reduction throughout the flow, and power-aware clock tree synthesis. Features and Benefits Low Power UPF 2.0 (IEEE 1801) based multi voltage flow Support for gas station methodology and always-on-buffering Power-aware buffering and sizing Power state table (PST) based advanced buffering Support for level shifters, isolation cells, and retention registers Distributed and ring style multi-threshold (MTCMOS) switch cell insertion Hierarchical UPF support Concurrent multi-Vt optimization Power aware CTS featuring cloning, restructuring, and slew shaping Concurrent power and timing optimization for all corner/mode/power scenarios Capacity Compact database and flexible architecture Ability to handle 100+ million instance designs Flexible abstraction capabilities including SI-ILM, HTP, and black boxes Unique synchronized optimization at the top-level design Advanced memory reduction technologies Design planning including flat, hierarchical, and pseudo flat floorplanning Support for both channel-less and channel-based flows Timing and congestion aware pin placement and feed-through insertion Data flow graph driven automatic macro placement Design planning including flat, hierarchical, and pseudo flat floorplanning Support for both channel-less and channel-based flows Timing and congestion aware pin placement and feed-through insertion Data flow graph driven automatic macro placement TAT Reduction Distributed and multithreaded analysis and optimization engines Signoff physical verification during implementation with Calibre InRoute Minimal ECO iterations through MCMM optimization Signoff quality built-in timing and extraction engines Industry’s first multi-threaded timing engine Advanced Nodes Comprehensive multi patterning and FinFET support Native coloring, verification and conflict resolution engines DRC, double/multi patterning, and DFM rule support for all leading foundries Pattern matching and recommended rules support Variation-aware timing and SI driven routing Automated, intelligent prevention of DRC/DFM issues Integrated Calibre sign-off engines for sign-off physical verification Automatic fixing of DRC and DFM violations during physical design Area Reduction Unified global router based congestion modeling Automated Channel-less floorplanning flow Intelligent white space management Precision DP fixing for minimal perturbation Dynamic area recovery throughout the flow Proprietary density management technology Design Planning Design planning including flat, hierarchical and pseudo flat floorplanning Timing and congestion aware pin placement and feed through insertion Data flow graph driven automatic macro placement Timing driven placement engine for optimal QoR Powerful and efficient GUI

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