Sentaurus Process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies. Created by combining the best-in-class features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabili.....
Language : english Authorization: Retail Freshtime：2008-04-21 Size: 690MB
::::::English Description:::::: HSPICE is the industry s gold standard for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With over 25 years of successful design tapeouts, HSPICE is the industry s most trusted and .....
Language : english Authorization: Retail Freshtime：2008-03-31 Size: 93MB
::English Description::::::TetraMAX® ATPG automatically generates high quality manufacturing test vectors. TetraMAX is the only ATPG solution optimized for a wide range of test methodologies that抯 integrated with Synopsys?DFT MAX, the leading test synthesis tool. The unparalleled ease-of-use.....
Language : english Authorization: Retail Freshtime：2008-02-20 Size: 51MB
Installing the Software by EST
Download the CosmosScope release to a temporary directory. You can obtain
the latest CosmosScope download instructions from the SolvNet Release
Library.
To install the software on UNIX systems,
1. Double-click the downloaded file, or enter the file name at the command
.....
Language : english Authorization: Pre Release Freshtime：2008-01-24 Size: 66MB
:::::English Description::::::Innovator is a powerful, fully integrated tool environment for developing, running and debugging virtual platforms. It comes with full SystemC™ (IEEE 1666) support. Its main components are: Schematic system editor, to instantiate, configure and connect IP model com.....
Language : english Authorization: Pre Release Freshtime：2007-12-14 Size: 59MB
Synopsys公司发布的针对65nm 和 45nm 设计的电子类软件cadabra。 ::::::English Description::::::Library developers are facing increasing challenges at the 65nm and 45nm nodes, including increasing design rule complexity, time-to-market pressures, library richness, and late design rule changes. Manua.....
Language : english Authorization: Pre Release Freshtime：2007-10-03 Size: 40MB
::::::English Description::::::Synopsys?TechXpress™ products enable a revolutionary amount of process insight in a minimum amount of silicon area that is not possible with conventional characterization technologies. A decade of experience in leading-edge technology development and yield optimi.....
Language : english Authorization: Pre Release Freshtime：2007-10-03 Size: 90MB
::::::English Description::::::IC WorkBench (ICWB) is a powerful, hierarchical layout visualization and analysis tool with GDSII/OASIS viewing, layout editing, and high-speed lithography simulation and analysis. IC WorkBench is designed to address a variety of lithographic applications including: Ma.....
Language : english Authorization: Pre Release Freshtime：2007-10-03 Size: 24MB
在采用现有 IP核创建系统级芯片(SoC)时，关键是在设计周期之初，在目标环境中快速地配置和验证IP核。在采用多个IP模块和诸如AMBA的芯片级总线进行设计创建时，设计人员需要能够轻易地完成将多个IP模块连接到总线上并进行配置，从而能够将精力集中在设计中新的逻辑电路上。采用了DesignWare IP 重用工具，IP的创建者可以将自己的IP.....
Language : English Authorization: Pre Release Freshtime：2007-09-08 Size: 44MB
Overview
Today’s complex integrated circuit (IC) designs generate a vast amount of simulation data. CosmosScope™ turns that mountain of data into useful information. With powerful analysis and measurement capabilities, patented waveform-calculator technology, and scripting language based o.....
Language : english Authorization: Pre Release Freshtime：2007-05-05 Size: 68MB
Synopsys, Inc. today announced that UMC has adopted Synopsys TetraMAX diagnostics to accelerate yield learning for designs that utilize the Synopsys DFT MAX scan compression automation solution. Rapid yield learning depends on the accuracy and efficiency of failure analysis, a manually intensive and.....
Language : english Authorization: Retail Freshtime：2007-05-03 Size: 102MB
:::::English Description::::::Synopsys?JupiterXT™ design planning solution enables fast feasibility analysis for a preview of implementation results, and provides detailed floor planning capabilities for flat or hierarchical physical design implementation styles. Project leaders and physical d.....
Language : english Authorization: Retail Freshtime：2007-05-03 Size: 227MB
As technology feature sizes shrink, conductors get smaller, and supply voltages reduce, the corresponding current per scaled feature size increases exponentially. These changes cause power-rail IR (voltage) drop and electromigration (EM) effects that significantly degrade performance and might cause.....
Language : english Authorization: Retail Freshtime：2007-05-03 Size: 161MB
Synopsys CoCentric System Studio 2006.12 SP1是一个功能强大的系统级设计环境，主要用于面向创新性SoC设计中算法和系统架构的两个至关重要的系统级设计领域。算法设计涵盖了信号处理，例如移动通信、多媒体编码解码器、DSL和调制解调器。架构设计把正确的处理器、定制逻辑电路、总线、内存和外设相结合，以确保芯片得到最有.....
Language : English Authorization: Retail Freshtime：2007-04-14 Size: 277MB
ynopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design plat.....
Language : english Authorization: Retail Freshtime：2007-04-14 Size: 103MB
Raphael NXT is a true three-dimensional (3D) capacitance extractor that provides silicon-accurate self and coupling capacitances for IC design. Equipped with an ultrafast extraction engine, Raphael NXT complements Star-RCXT by extracting 3D capacitances of critical nets, cells, or blocks on the f.....
Language : English Authorization: Retail Freshtime：2007-04-14 Size: 10MB
。Complete and accurate cell characterization is essential for automated implementation and verification of complex system-on-chips (SoC). Capturing sufficiently accurate timing, power and signal integrity information, as well as operating condition variability for 90-nm and 65-nm technologies requi.....
Language : english Authorization: Retail Freshtime：2007-04-11 Size: 50MB
::::::HSIMplusHSIMplus™ 2007.03 is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simulators, by providing a complete.....
Language : english Authorization: Retail Freshtime：2007-04-11 Size: 19MB
::::::English Description::::::HSIMplusHSIMplus™ 2007.03 Linux is a fully-integrated suite of tools for the design and verification of nanometer ICs, built upon the production-proven HSIM hierarchical Fast-SPICE simulator. HSIMplus exceeds the capabilities of competitor’s Fast-SPICE simu.....
Language : english Authorization: Retail Freshtime：2007-04-11 Size: 90MB
::::::English Description::::::Synopsys’ Leda® 2007.03 is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda抯 pre.....
Language : english Authorization: Retail Freshtime：2007-03-13 Size: 103MB
Synopsys Online Documentation——Synopsys的在线文档。::::::English Description::::::SOLID E3-Dimensional Optical Lithography SimulationSOLID E is a window-based software package for simulating and modeling all the processes and techniques involved in optical microlithography. It is able.....
Language : english Authorization: Retail Freshtime：2007-03-13 Size: 998MB
The DesignWare Library provides a comprehensive portfolio of synthesizable and verification IP including an AMBA-based on-chip bus solution, memory IP, popular processor cores, bus and I/O standards, and performance enhancing datapath IP elements.
The following product documentation is for the .....
Language : english Authorization: Retail Freshtime：2007-03-05 Size: 101MB
Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, announced the availability of advanced device parameter measurement functionality in its Hercules(TM) Physical Verification Suite (PVS). Developed to support the latest release of 65-nanometer (nm) design kits from IBM (N.....
Language : english Authorization: Retail Freshtime：2007-02-04 Size: 194MB